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march 2004 dsc-6111/00 ?2003 integrated device technology, inc. qdr srams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, and micron techno logy, inc. 1 18mb pipelined qdr?ii sram burst of 4 advance information idt71p74204 idt71p74104 idt71p74804 idt71p74604 features u 18mb density (2mx8, 2mx9, 1mx18, 512kx36) u separate, independent read and write data ports - supports concurrent transactions u dual echo clock output u 4-word burst on all sram accesses u multiplexed address bus one read or one write request per clock cycle u ddr (double data rate) data bus - four word burst data per two clock cycles on each port - four word transfers per clock cycle u depth expansion through control logic u hstl (1.5v) inputs that can be scaled to receive signals from 1.4v to 1.9v. u scalable output drivers - can drive hstl, 1.8v ttl or any voltage level from 1.4v to 1.9v. - output impedance adjustable from 35 ohms to 70 ohms u 1.8v core voltage (v dd ) u 165-ball, 1.0mm pitch, 15mm x 17mm fbga package u jtag interface description the idt qdrii tm burst of four srams are high-speed synchronous memories with independent, double-data-rate (ddr), read and write data ports. this scheme allows simultaneous read and write access for the maximum device throughput, with four data items passed with each read or write. four data word transfers occur per clock cycle, providing quad-data-rate (qdr) performance. comparing this with standard sram common i/o (cio), single data rate (sdr) devices, a four to one in- crease in data access is achieved at equivalent clock speeds. consider- ing that qdrii allows clock speeds in excess of standard sram de- vices, the throughput can be increased well beyond four to one in most applications. using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. all buses associated with the qdrii are unidirectional and can be optimized for signal integrity at very high bus speeds. the qdrii has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. the qdrii has a single sdr address bus with read addresses and write addresses multiplexed. the read and write addresses interleave with each occurring a maximum of every other cycle. in the event that no operation takes place on a cycle, the subsequest cycle may begin with either a read or write. during write operations, the writing of individual bytes may be blocked through the use of byte or nibble write control signals. the qdrii has echo clocks, which provide the user with a clock functional block diagram data reg add reg ctrl logic clk gen ( note1 ) d ( note2 ) sa r w ( note3 ) bw x k k c c select output control w r it e /r e a d d e c o d e s e n s e a m p s o u t p u t r e g o u t p u t s e l e c t write driver ( note2 ) cq q ( note1 ) 18m memory array cq notes 1) represents 8 data si g nal lines for x8, 9 si g nal lines for x9, 18 si g nal lines for x18, and 36 si g nal lines for x36 2) represents 19 address si g nal lines for x8 and x9, 18 address si g nal lines for x18, and 17 address si g nal lines for x36. 3) represents 1 si g nal line for x9, 2 si g nal lines for x18, and four si g nal lines for x36. on x8 parts, the bw is a nibble write andthereare2si g nal lines. o u t p u t s e l e c t 6111 drw16
6.42 2 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range edge of cq, and the falling edge of cq . the rising edge of c generates the rising edge of cq and the falling edge of cq. this scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. the echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. read and write operations qdrii devices internally store the 4 words of the burst as a single, wide word and will retain their order in the burst. there is no ability to address to the single word level or reverse the burst order; however, the byte and nibble write signals can be used to prevent writing any indi- vidual bytes, or combined to prevent writing one word of the burst. read and write operations may be interleaved with each occurring on every other clock cycle. in the event that two reads or two writes are requested on adjacent clock cycles, the operation in progress will com- plete and the second request will be ignored. in the event that both a read and write are requested simultaneously, the read operation will win and the write operation will be ignored. read operations are initiated by holding the read port select ( r ) low, and presenting the read address to the address port during the rising edge of k which will latch the address. the data will then be read and will appear at the device output at the designated time in correspondence with the c and c clocks. write operations are initiated by holding the write port select ( w ) low and presenting the designated write address to the address bus. the qdrii sram will receive the address on the rising edge of clock k . on the following rising edge of k clock, the qdrii sram will receive the first data item of the four word burst on the data bus. along with the data, the byte ( bw ) or nibble write ( nw ) inputs will be accepted, indicating which bytes of the data inputs should be written to the sram. on the rising edge of k, the next word of the write burst and bw / nw will be accepted. the following k and k will receive the last two words of the four word burst, with their bw / nw enables. output enables the qdrii sram automatically enables and disables the q[x:0] outputs. when a valid read is in progress, and data is present at the output, the output will be enabled. if no valid data is present at the output (read not active), the output will be disabled (high impedance). the echo clocks will remain valid at all times and cannot be disabled or turned off. during power-up the q outputs will come up in a high impedance state. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and vss to allow the sram to adjust its output drive imped- ance. the value of rq must be 5x the value of the intended drive impedance of the sram. the allowable range of rq to guarantee impedance matching with a tolerance of +/- 10% is between 175 ohms and 350 ohms, with v ddq = 1.5v. the output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and tem- perature. if the user wishes to drive the output impedance of the sram to its lowest value, the zq pin may be tied to v ddq . the device is capable of sustaining full bandwidth on both the input and output ports simultaneously. all data is in two word bursts, with addressing capability to the burst level. clocking the qdrii sram has two sets of input clocks, namely the k, k clocks and the c, c clocks. in addition, the qdrii has an output echo clock, the k and k clocks are the primary device input clocks. the k clock is, used to clock in the control signals ( r , w and bw x/ nw x), the ad- dress, first and third words of the data burst during a write operation. the k clock is used to clock in the control signals ( bw x or nw x) and the second and fourth words of the data burst during a write operation. the k and k clocks are also used internally by the sram. in the event that the user disables the c and c clocks, the k and k clocks will be used to clock the data out of the output register and generate the echo clocks. the c and c clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. c and c must be presented to the sram within the timing tolerances. the output data from the qdrii will be closely aligned to the c and c input, through the use of an internal dll. when c is presented to the qdrii sram, the dll will have already internally clocked the data to arrive at the device output simultaneously with the arrival of the c clock. the c and second data item of the burst will also correspond. the third and fourth data items will follow on the next clock cycle. single clock mode the qdrii sram may be operated with a single clock pair. c and c may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the k and k clocks. dll operation the dll in the output structure of the qdrii sram can be used to closely align the incoming clocks c and c with the output of the data, generating very tight tolerances between the two. the user may disable the dll by holding doff low. with the dll off, the c and c (or k and k if c and c are not used) will directly clock the output register of the sram. with the dll off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. echo clock the echo clocks, cq and cq , are generated by the c and c clocks (or k, k if c, c are disabled). the rising edge of c generates the rising that is precisely timed to the data output, and tuned with matching imped- ance and signal quality. the user can use the echo clock for down- stream clocking of the data. echo clocks eliminate the need for the user to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. since the echo clocks are generated by the same source that drives the data output, the relationship to the data is not significantly affected by voltage, temperature and process, as would be the case if the clock were generated by an outside source. all interfaces of the qdrii sram are hstl, allowing speeds beyond sram devices that use any form of ttl interface. the interface can be scaled to higher voltages (up to 1.9v) to interface with 1.8v systems if necessary. the device has a v ddq and a separate vref, allowing the user to designate the interface operational voltage, independent of the device core voltage of 1.8v v dd . the output impedance control allows the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. cq, cq .
6.42 3 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range symbol pin function description d[x:0] input synchronous data input signals, sampled on the rising edge of k and k clocks during valid write operations 2m x 8 -- d[7:0] 2m x 9 -- d[8:0] 1m x 18 -- d[17:0] 512k x 36 -- d[35:0] bw 0 , bw 1 bw 2 , bw 3 input synchronous byte write select 0, 1, 2, and 3 are active low. sampled on the rising edge of the k and again on the rising edge of k clocks during write operations. used to select which byte is written into the device during the current portion of the write operations. bytes not written remain unaltered. all the byte writes are sampled on the same edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written in to the device. 2m x 9 -- bw 0 controls d[8:0] 1m x 18 -- bw 0 controls d[8:0] and bw 1 controls d[17:9] 512k x 36 -- bw 0 controls d[8:0], bw 1 controls d[17:9], bw 2 controls d[26:18] and bw 3 controls d[35:27] nw 0, nw 1 input synchronous nibble write select 0 and 1 are active low. available only on x8 bit parts instead of byte write selects. sampled on the rising edge of the k and k clocks during write operations. used to select which nibble is written into the device during the current portion of the write operations. nibbles no t written remain unaltered. all the nibble writes are sampled on the same edge as the data. deselecting a nibble write select will cause the corresponding nibble of data to be ignored and not written in to the device. sa input synchronous address inputs are sampled on the rising edge of k clock during active read or write operations. these address inputs are multiplexed so a read and write can be initiated on alternate clock cycles. these inputs are ignored when the appropriate port is deselected. q[x:0] output synchronous data output signals. these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations or k and k when operating in single clock mode. when the read port is deselected, q[x:0] are automatically three-stated. w input synchronous write control logic active low. sampled on the rising edge of the positive input clock (k). when asserted active, a write operation in initiated. deasserting will deselect the write port, causing d[x:0] to be ignored. if a write operation has successfully been initiated, it will continue to completion, ignoring the w on the following clock cycle. this allows the user to continuously hold w low while bursting data into the sram. r input synchronous read control logic, active low. sampled on the rising edge of positive input clock (k). when active, a read operation is initiated. deasserting will cause the read port to be deselected. when deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the c clock. each read access consists of a burst of four sequential transfer. if a read operation has successfully been initiate d, it will continue to completion, ignoring the r on the following clock cycle. this allows the user to continuously hold r low while bursting data fro m the sram. c inp ut clock po sitive output clo ck input. c is used in conjunction with c to clo ck out the re ad data from the de vice . c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. c inp ut clock ne gative o utput clock input. c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the flight times of various devices on the board back to the controller. see application example for further details. k input clock positive input clock input. the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q[x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k inp ut clock negative input clock input. k is used to capture synchronous inputs being presented to the device and to drive out data through q[x:0] when in single clock mode. cq, cq output clock synchronous echo clock outputs. the rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. these signals are free running and do not stop when the output data is three- stated. zq inp ut output imp edance matching input. this input is us ed to tune the d evice o utputs to the sys tem data bus imped ance. q[x:0] output impedance is set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternately, this pin can be connected directly to v ddq, which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. 6111 tbl 02a pin definitions
6.42 4 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range symbol pin function description doff input dll turn off. when low this input w ill turn off the dll inside the device. the ac timings with the dll turned off will be different from those listed in this data sheet. there will be an increased propagation delay from the incidence of c and c to q, or k and k to q as configured. the propagation delay is not a tested parameter, but will be similar to the propagation delay of other sram devices in this speed grade. tdo output tdo p in fo r jtag. tck input tck pin for jtag. tdi input tdi pin for jtag. an internal resistor will pull tdi to v dd when the pin is unconnected. tms input tms pin for jtag. an internal resistor will pull tms to v dd when the pin is unconnected. nc no connect no connec ts inside the package. can be tied to any voltage level v ref input reference reference voltage input. static input used to set the reference le vel for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device. should be connected to a 1.8v power supply. v ss ground ground for the device. should be connected to ground of the system. v ddq power supply power supply for the outputs of the device. should be connected to a 1.5v power supply for hstl or scaled to the desired output voltage. 6111 tbl 02b pin definitions continued
6.42 5 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range pin configuration 2m x 8 1234567891011 a cq v ss / sa (2) sa wnw 1 k nc r sa v ss/ sa (1) cq b nc nc nc sa nc k nw 0 sa nc nc q 3 c nc nc nc v ss sa nc sa v ss nc nc d 3 d nc d 4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q 4 v ddq v ss v ss v ss v ddq nc d 2 q 2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d 5 q 5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q 1 d 1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q 6 d 6 v ddq v ss v ss v ss v ddq nc nc q 0 m nc nc nc v ss v ss v ss v ss v ss nc nc d 0 n nc d 7 nc v ss sa sa sa v ss nc nc nc p nc nc q 7 sa sa c sa sa nc nc nc r tdo tck sa sa sa c sa sa sa tms tdi 6111 tbl 12 165-ball fbga pinout top view notes: 1. a10 is reserved for the 36mb expansion address. 2. a2 is reserved for the 72mb expansion address.
6.42 6 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range pin configuration 2m x 9 1234567891011 a cq v ss/ sa (2) sa w nc k nc r sa v ss/ sa (1) cq b nc nc nc sa nc k bw sa nc nc q 3 c nc nc nc v ss sa nc sa v ss nc nc d 3 d nc d 4 nc v ss v ss v ss v ss v ss nc nc nc e nc nc q 4 v ddq v ss v ss v ss v ddq nc d 2 q 2 f nc nc nc v ddq v dd v ss v dd v ddq nc nc nc g nc d 5 q 5 v ddq v dd v ss v dd v ddq nc nc nc h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc nc v ddq v dd v ss v dd v ddq nc q 1 d 1 k nc nc nc v ddq v dd v ss v dd v ddq nc nc nc l nc q 6 d 6 v ddq v ss v ss v ss v ddq nc nc q 0 m nc nc nc v ss v ss v ss v ss v ss nc nc d 0 n nc d 7 nc v ss sa sa sa v ss nc nc nc p nc nc q 7 sa sa c sa sa nc d 8 q 8 r tdo tck sa sa sa c sa sa sa tms tdi 6111 tb l 1 2a 165-ball fbga pinout top view notes: 1. a10 is reserved for the 36mb expansion address. 2. a2 is reserved for the 72mb expansion address.
6.42 7 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range pin configuration 1m x 18 1234567891011 a cq v ss/ sa (3) nc/ sa (1) wbw 1 k nc r sa v ss/ sa (2) cq b nc q 9 d 9 sa nc k bw 0 sa nc nc q 8 c nc nc d 10 v ss sa nc sa v ss nc q 7 d 8 d nc d 11 q 10 v ss v ss v ss v ss v ss nc nc d 7 e nc nc q 11 v ddq v ss v ss v ss v ddq nc d 6 q 6 f nc q 12 d 12 v ddq v dd v ss v dd v ddq nc nc q 5 g nc d 13 q 13 v ddq v dd v ss v dd v ddq nc nc d 5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d 14 v ddq v dd v ss v dd v ddq nc q 4 d 4 k nc nc q 14 v ddq v dd v ss v dd v ddq nc d 3 q 3 l nc q 15 d 15 v ddq v ss v ss v ss v ddq nc nc q 2 m nc nc d 16 v ss v ss v ss v ss v ss nc q 1 d 2 n nc d 17 q 16 v ss sa sa sa v ss nc nc d 1 p nc nc q 17 sa sa c sa sa nc d 0 q 0 r tdo tck sa sa sa c sa sa sa tms tdi 6111 tbl 12b 165-ball fbga pinout top view notes: 1. a3 is reserved for the 36mb expansion address. 2. a10 is reserved for the 72mb expansion address. this must be tied or driven to v ss on the 1m x 18 qdrii burst of 4 (71p74804) devices. 3. a2 is reserved for the 144mb expansion address. this must be tied or driven to v ss on the 1m x 18 qdrii burst of 4 (71p74804) devices.
6.42 8 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range pin configuration 512k x 36 165-ball fbga pinout top view 1234567891011 a cq v ss / sa (4) nc/ sa (2) wbw 2 kbw 1 r nc/ sa (1) v ss sa (3) cq b q 27 q 18 d 18 sa bw 3 k bw 0 sa d 17 q 17 q 8 c d 27 q 28 d 19 v ss sa nc sa v ss d 16 q 7 d 8 d d 28 d 20 q 19 v ss v ss v ss v ss v ss q 16 d 15 d 7 e q 29 d 29 q 20 v ddq v ss v ss v ss v ddq q 15 d 6 q 6 f q 30 q 21 d 21 v ddq v dd v ss v dd v dd q d 14 q 14 q 5 g d 30 d 22 q 22 v ddq v dd v ss v dd v ddq q 13 d 13 d 5 h doff v ref v dd q v ddq v dd v ss v dd v ddq v dd q v ref zq j d 31 q 31 d 23 v ddq v dd v ss v dd v ddq d 12 q 4 d 4 k q 32 d 32 q 23 v ddq v dd v ss v dd v ddq q 12 d 3 q 3 l q 33 q 24 d 24 v ddq v ss v ss v ss v ddq d 11 q 11 q 2 m d 33 q 34 d 25 v ss v ss v ss v ss v ss d 10 q 1 d 2 n d 34 d 26 q 25 v ss sa sa sa v ss q 10 d 9 d 1 p q 35 d 35 q 26 sa sa c sa sa q 9 d 0 q 0 r tdo tck sa sa sa c sa sa sa tms tdi 6111 tbl 12c notes: 1. a9 is reserved for the 36mb expansion address. 2. a3 is reserved for the 72mb expansion address. 3. a10 is reserved for the 144mb expansion address. this must be tied or driven to v ss on the 512k x 36 qdrii burst of 4 (71p74604) devices. 4. a2 is reserved for the 288mb expansion address. this must be tied or driven to v ss on the 512k x 36 qdrii burst of 4 (71p74604) devices.
6.42 9 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range absolute maximum ratings (1) (2) capacitance (t a = +25c, f = 1.0mhz) (1) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v ddq must not exceed v dd during normal operation. note: 1. tested at characterization and retested after any design or process change that may affect these parameters. symbol parameter conditions max. unit c in input capacitance v dd = 1.8v v ddq = 1.5v 5pf c clk clock input capacitance 6 pf c o output capacitance 7 pf 6111 tbl 06 symbol rating value unit v te rm supply voltage on v dd with resp ect to gnd C0.5 to +2.9 v v te rm supply voltage on v ddq with resp ect to gnd C0.5 to v dd +0.3 v v te rm volta ge o n input te rminals with respect to gnd C0.5 to v dd +0.3 v v te rm voltage on output and i/o te rm inals with re sp ect to gnd. C0.5 to v ddq +0.3 v t bias temperature under bias C55 to +125 c t stg storage temperature C65 to +150 c i out continuous current into outputs + 20 ma 6111 tb l 05 recommended dc operating and temperture conditions symbol parameter min. typ. max. unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 1.9 v v ss ground 0 0 0 v v ref input reference voltage 0.68 v ddq /2 0.95 v t a ambient temperature (1) 025+70 o c 6111 tbl 04 notes: 1) all byte write ( bw x) and nibble write ( nw x) signals are sampled on the rising edge of k and again on k . the data that is present on the data bus in the designated byte/nibble will be latched into the input if the corresponding bw x or nw x is held low. the rising edge of k will sample the first and third bytes/ nibbles of the four word burst and the rising edge of k will sample the second and fourth bytes/nibbles of the four word burst. 2) the availability of the bw x or nw x on designated devices is described in the pin description table. 3) the qdrii burst of four sram has data forwarding. a read request that is initiated on the cycle following a write request to the same address will produce the newly written data in response to the read request. signal bw 0 bw 1 bw 2 bw 3 nw 0 nw 1 write byte 0 lxxxxx write byte 1 x l x x x x write byte 2 x x l x x x write byte 3 xxxlxx write nibble 0 x x x x l x write nibble 1 xxxxxl 6111 tbl 09 write descriptions (1,2) note: 1. during production testing, the case temperarure equals the ambient temperature.
6.42 10 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range application example sram #1 sa wbw 0 bw 1 c q zq 250 w r d k k c data in r memory controller return clk source clk return clk source clk r=50 w r v t =v ref r 6111 drw 20 v t w address data out r v t r v t r sram #4 sa wbw 0 bw 1 c q zq 250 w r d k k c w bwx / nwx r r r v t
6.42 11 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range dc electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8 100mv, v ddq = 1.4v to 1.9v) parameter symbol test conditions min max unit note input leakage current i il v dd = max v in = v ss to v dd q -10 +10 m a output leakage current i ol output disabled -10 +10 m a operating current (x36,x18,x9,x8): ddr i dd v dd = max, i out = 0ma (outputs open), cycle time > t khkh min 333mh z - tb d ma 1 300mh z - tb d 250mh z - tb d 300mhz - tb d 167mhz - tb d standby current: nop i sb1 device deselected (in nop state) i out = 0ma (outputs open), f= m ax, a ll inp uts < 0.2v or > vdd -0.2v 333mh z - tb d ma 2 300mh z - tb d 250mh z - tb d 200mhz - tb d 167mhz - tb d output high voltage v oh1 rq = 250 w, i oh = -15ma v dd q /2-0.12 v dd q /2+0.12 v 3,7 output low voltage v ol1 rq = 250 w, i ol = 15ma v dd q /2-0.12 v dd q /2+0.12 v 4,7 output high voltage v oh2 i oh = -0.1ma v dd q -0.2 v dd q v 5 output low voltage v ol2 i ol = 0.1ma v ss 0.2 v 6 6111 tb l 10 c notes: 1. operating current is measured at 100% bus utilization. 2. standby current is only after all pending read and write burst operations are completed. 3. outputs are impedance-controlled. i oh = -(v ddq /2)/(rq/5) and is guaranteed by device characterization for 175 w < rq < 350 w. this parameter is tested at rq = 250 w, which gives a nominal 50 w output impedance. 4. outputs are impedance-controlled. i ol = (v ddq /2)/(rq/5) and is guaranteed by device characterization for 175 w < rq < 350 w. this parameter is tested at rq = 250 w, which gives a nominal 50 w output impedance. 5. this measurement is taken to ensure that the output has the capability of pulling to the v ddq rail, and is not intended to be used as an impedance measurement point. 6. this measurement is taken to ensure that the output has the capability of pulling to v ss , and is not intended to be used as an impedance measurement point. 7. programmable impedance mode.
6.42 12 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range parameter symbol min max unit notes input high voltage, dc v ih (dc ) v ref +0.1 v ddq +0.3 v 1,2 input low voltage, dc v il (dc) -0.3 v ref -0.1 v 1,3 input high voltage, ac v ih (ac) v ref +0.2 - v 4,5 input low voltage, ac v il (ac) - v ref -0.2 v 4,5 6111 tb l 10d input electrical characteristics over the operating temperature and supply voltage range (v dd = 1.8 100mv, v ddq = 1.4v to 1.9v) 1. these are dc test criteria. dc design criteria is v ref + 50mv. the ac v ih /v il levels are defined separately for measuring timing parameters. 2. v ih (max) dc = v ddq +0.3, v ih (max) ac = v dd +0.5v (pulse width <20% tkhkh (min)) 3. v il (min) dc = -0.3v, v il (min) ac = -0.5v (pulse width <20% tkhkh (min)) 4. this conditon is for ac function test only, not for ac parameter test. 5. to maintain a valid level, the transitioning edge of the input must: a) sustain a constant slew rate from the current ac level through the target ac level, v il (ac) or v ih (ac) b) reach at least the target ac level. c) after the ac target level is reached, continue to maintain at least the target dc level, v il (dc) or v ih (dc) notes : ac test load device r l =50 w z 0 =50 w v ddq /2 under test 0.75v v ref output 6111 drw 04 zq r q = 250 w ac test conditions parameter symbol value unit core power supply voltage v dd 1.7-1.9 v output power supply voltage v ddq 1.4-1.9 v input high/low level v ih /v il 1.25/0.25 v input reference level vref 0.75 v inp ut rise /fall time tr/tf 0.6/0.6 ns output timing reference level v ddq /2 v 6111tbl 11a note: 1. parameters are tested with rq=250 w 1.25v 0.25v 6111 drw 06 0.75v v i l v d d v d d +0.25 v d d +0.5 20% tkhkh (min) 6111 drw 21 v ss v ih v ss -0.25v v ss -0.5v 20% tkhkh (min) 6111 drw 22 overshoot timing undershoot timing
6.42 13 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range ac electrical characteristics (v dd = 1.8 100mv, v ddq = 1.4v to 1.9v,t a = 0 to 70c) (3,8) symbol parameter 333mhz 300mhz 250mhz 200mhz 167mhz unit notes min. max min. max min. max min. max min. max clock parameters t khkh average clock cycle time (k , k ,c,c) 3.00 3.47 3.30 5.25 4.00 6.30 5.00 7.88 6.00 8.40 ns t kc var cy cle to cycle period jitter (k, k ,c, c ) - 0.20 - 0.20 - 0.20 - 0.20 - 0.20 ns 1,5 t khkl clock high time (k, k ,c, c ) 1.20 - 1.32 - 1.60 - 2.00 - 2.40 - ns 9 t klkh clock low time (k, k ,c, c ) 1.20 - 1.32 - 1.60 - 2.00 - 2.40 - ns 9 t kh k h clock to clock (k ? k ,c ? c ) 1.35 - 1.49 - 1.80 - 2.20 - 2.70 - ns 10 t k hkh cl oc k to clock ( k ? k, c ? c) 1.35 - 1.49 - 1.80 - 2.20 - 2.70 - ns 10 t khch clock to data clock (k ? c, k ? c ) 0.00 1.30 0.00 1.45 0.00 1.80 0.00 2.30 0.00 2.80 ns t kc lock dll lock time (k, c) 1024 - 1024 - 1024 - 1024 - 1024 - cycles 2 t kc reset k static to dll reset 30 - 30 - 30 - 30 - 30 - ns output parameters t chqv c, c high to output valid - 0.45 - 0.45 - 0.45 - 0.45 - 0.50 ns 3 t chqx c, c high to output hold -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3 t chcqv c, c high to echo clock valid - 0.45 - 0.45 - 0.45 - 0.45 - 0.50 ns 3 t chcqx c, c high to echo clock hold -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3 t cq hqv cq, cq high to output valid - 0.25 - 0.27 - 0.30 - 0.35 - 0.40 ns t cqhqx cq, cq high to output hold -0.25 - -0.27 - -0.30 - -0.35 - -0.40 - ns t chqz c high to output high-z - 0.45 - 0.45 - 0.45 - 0.45 - 0.50 ns 3,4,5 t chqx1 c high to output low-z -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3,4,5 set-up times t avkh address valid to k, k rising edge 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 6 t iv kh control inputs valid to k, k rising edge 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 7 t dv kh date-in valid to k, k rising edge 0.30 - 0.30 - 0.35 - 0.40 - 0.50 - ns hold times t khax k, k rising edge to address hold 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 6 t khix k, k rising edge to control inputs hold 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 7 t khdx k, k rising edge to data-in hold 0.30 - 0.30 - 0.35 - 0.40 - 0.50 - ns 6111 tbl 11 notes: 1. cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per jedec standard no.65 (eia/jesd65) pg.10 2. v dd slew rate must be less than 0.1v dc per 50 ns for dll lock retention. dll lock time begins once vdd and input clock are stabl e. 3. if c, c are tied high, k, k become the references for c, c timing parameters. 4. to avoid bus contention, at a given voltage and temperature tchqx 1 is bigger than tchqz. the specs as shown do not imply bus contention because tchqx1 is a min parameter that is worse case at totally different te st conditions (0c, 1.9v) than tchqz, which is a max parameter (worst case at 70c, 1.7v) it is not possible for two srams on the same board to be at such different voltage and temperature. 5. this parameter is guaranteed by device characterization, but not production tested. 6. all address inputs must meet the specified setup and hold times for all latching clock edges. 7. control signals are r , w , bw 0 , bw 1 and ( nw 0 , nw 1 , for x8) and ( bw 2 , bw 3 also for x36) 8. during production testing, the case temperature equals t a. 9. clock high time (tkhkl) and clock low time (tklkh) should be within 40% to 60% of the cycle time (tkhkh). 10. clock to clock time (tkh k h) and clock to clock time (t k hkh) should be within 45% to 55% of the cycle time (tkhkh).
6.42 14 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range timing waveform of combined read and write cycles k k 1 2 3 r sa q tkhch t k h k l t k h i x t i v k h t k h a x t a v k h c c cq cq tchqx tchqx1 tklkh tchcqv tchcqx w d t d v k h t d v k h 4 5 67 t k l k h t k h k h t k h k h a2 a1 a0 a3 t k h d x t k h d x d10 d12 qx3 tchqv tchqv tchqx tcqhqv tkhch tkhkh tkh k h tkhkl tchcqx tchcqv nop read a0 write a1 write a3 read a2 nop t k h i x t i v k h d11 d13 d30 d32 d31 d33 qx2 q00 q01 q02 q03 q20 q21 q22 q23 tchqz nop 6 1 1 1 d r w 0 9 . tcqhqx
6.42 15 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range ieee 1149.1 test access port and boundary scan-jtag this part contains an ieee standard 1149.1 compatible test access port (tap). the package pads are monitored by the serial sca n circuitry when in test mode. this is to support connectivity testing during manufacturing and system diagnostics. in conformance with i eee 1149.1, the sram contains a tap controller, instruction register, bypass register and id register. the tap controller has a standard 16-st ate machine that resets internally upon power-up; therefore, the trst signal is not required. it is possible to use this device without utilizi ng the tap. to disable the tap controller without interfacing with normal operation of the sram, tck must be tied to vss to preclude a mid level input . tms and tdi are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnecte d, but they may also be tied to vdd through a register. tdo should be left unconnected. jtag block diagram jtag instruction coding ir2 ir1 ir0 instruction tdo output notes 0 0 0 extest boundary scan register 0 0 1 idcode identification register 2 0 1 0 sample-z boundary scan register 1 0 1 1 reserved do not use 5 1 0 0 sample/preload boundary scan register 4 1 0 1 reserved do not use 5 1 1 0 reserved do not use 5 1 1 1 bypass bypass register 3 6111tbl 13 notes: 1. places qs in hi-z in order to sample all input data regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initialized to vss when bypass instruction is invoked. the bypass register also holds serially loaded tdi when existing the shift dr states. 4. sample instruction does not place output pins in hi-z. 5. this instruction is reserved for future use. tap controller state diagram test logic reset run test idle select dr capture dr pause dr exit 2 dr update dr shift dr exit 1 dr select ir capture ir pause ir exit 2 ir update ir shift ir exit 1 ir 0 0 0 0 0 0 1 1 1 1 1 1 1 0 6111 drw 17 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 sram core bypass reg. identification reg. instruction reg . control signal s tap controller a,d k, k c,c q cq cq tdi tms tck tdo 6 1 1 1 d r w 1 8 s
6.42 16 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range part instrustion register bypass register id register boundry scan 512kx36 3 bits 1 bit 32 bits 107 bits 1mx18 3 bits 1 bit 32 bits 107 bits 2mx8/x9 3 bits 1 bit 32 bits 107 bits 6111 tbl 14 instruction field all devices description part number revision number (31:29) 000 revision number device id (28:12) 0 0000 0010 0100 0000 0 0000 0010 0100 0001 0 0000 0010 0100 0010 0 0000 0010 0100 0011 512kx36 qdrii burst of 4 1mx18 2mx9 2mx8 71p74604s 71p74804s 71p74104s 71p74204s idt jedec id code (11:1) 000 0011 0011 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. 6111 tbl 15 scan register definition identification register definitions
6.42 17 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range order pin id 16r 26p 36n 47p 57n 67r 78r 88p 99r 10 11p 11 10p 12 10n 13 9p 14 10m 15 11n 16 9m 17 9n 18 11l 19 11m 20 9l 21 10l 22 11k 23 10k 24 9j 25 9k 26 10j 27 11j 28 11h 29 10g 30 9g 31 11f 32 11g 33 9f 34 10f 35 11e 36 10e 6111 tbl 16a boundary scan exit order (2m x 8-bit, 2m x 9-bit) order pin id 37 10d 38 9e 39 10c 40 11d 41 9c 42 9d 43 11b 44 11c 45 9b 46 10b 47 11a 48 internal 49 9a 50 8b 51 7c 52 6c 53 8a 54 7a 55 7b 56 6b 57 6a 58 5b 59 5a 60 4a 61 5c 62 4b 63 3a 64 2a 65 1a 66 2b 67 3b 68 1c 69 1b 70 3d 71 3c 72 2d 6111 tb l 17a order pin id 73 3e 74 2c 75 1d 76 2e 77 1e 78 2f 79 3f 80 2g 81 3g 82 1f 83 1g 84 1j 85 2j 86 3k 87 3j 88 3l 89 2l 90 1k 91 2k 92 1m 93 1l 94 3n 95 3m 96 2n 97 3p 98 2m 99 1n 100 2p 101 1p 102 3r 103 4r 104 4p 105 5p 106 5n 107 5r 6111 tbl 18 a
6.42 18 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range boundary scan exit order (1m x 18-bit, 512k x 36-bit) order pin id 16r 26p 36n 47p 57n 67r 78r 88p 99r 10 11p 11 10p 12 10n 13 9p 14 10m 15 11n 16 9m 17 9n 18 11l 19 11m 20 9l 21 10l 22 11k 23 10k 24 9j 25 9k 26 10j 27 11j 28 11h 29 10g 30 9g 31 11f 32 11g 33 9f 34 10f 35 11e 36 10e 6111 tbl 16 order pin id 37 10d 38 9e 39 10c 40 11d 41 9c 42 9d 43 11b 44 11c 45 9b 46 10b 47 11a 48 internal 49 9a 50 8b 51 7c 52 6c 53 8a 54 7a 55 7b 56 6b 57 6a 58 5b 59 5a 60 4a 61 5c 62 4b 63 3a 64 1h 65 1a 66 2b 67 3b 68 1c 69 1b 70 3d 71 3c 72 1d 6111 tbl 17 order pin id 73 2c 74 3e 75 2d 76 2e 77 1e 78 2f 79 3f 80 1g 81 1f 82 3g 83 2g 84 1j 85 2j 86 3k 87 3j 88 2k 89 1k 90 2l 91 3l 92 1m 93 1l 94 3n 95 3m 96 1n 97 2m 98 3p 99 2n 100 2p 101 1p 102 3r 103 4r 104 4p 105 5p 106 5n 107 5r 6111 tb l 18
6.42 19 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range parameter symbol min ty p max unit note output power supply v ddq 1.4 - 1.9 v power supply voltage v dd 1.7 1.8 1.9 v in p u t h ig h l e v e l v ih 1.3 - v dd +0.3 v in p u t l o w le v e l v il -0.3 - 0.5 v output high voltage (ioh = -1ma) v oh v ddq - 0.2 - v ddq v 1 output low voltage (iol = 1m a) v ol v ss - 0.2 v 1 6111 tbl 19 parameter symbol min unit note input high/low level v ih /v il 1.3/0.5 v input rise/fall time tr/tf 1.0/1.0 ns inp ut and output timing reference level v ddq /2 v 1 6111 tbl 20 jtag dc operating conditions note: 1. the output impedance of tdo is set to 50 ohms (nominal process) and does not vary with the external resistor connected to z q. jtag ac test conditions parameter symbol min max unit note tck cycle time t chch 50 - ns tck high pulse width t chcl 20 - ns tck low pulse width t clch 20 - ns tms input setup time t mvch 5-ns tms input hold time t chmx 5-ns tdi input setup time t dv ch 5-ns tdi input hold time t chdx 5-ns sram input setup time t svch 5-ns sram input hold time t chsx 5-ns clock low to output valid t clqv 010ns 6111 tbl.21 jtag ac characteristics jtag timing diagram 6 1 1 1 d r w 1 9 tc k tm s t chch td i / sr a m inp u t s td o t mvch t dvch t svch t chcl t chmx t chdx t chsx t clch t clqv sr a m out p u t s note: 1. see ac test load on page 12.
6.42 20 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range package diagram outline for 165-ball fine pitch grid array
6.42 21 idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18-bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range ordering information corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408-492-8674 800-544-7726 www.idt.com qdr srams and quad data rate rams comprise a new family of products developed by cypress semiconductor, idt, and micron techno logy, inc. s power xxx speed bq package bq idt 71p74xxx 333 300 250 200 167 6111 drw 15 device type 165 fine pitch ball grid array (fbga) clock frequency in megahertz idt71p74204 2m x 8 qdr ii sram burst of 4 idt71p74104 2m x 9 qdr ii sram burst of 4 idt71p74804 1m x 18 qdr ii sram burst of 4 idt71p74604 512k x 36 qdr ii sram burst of 4 process temperature range blank commercial (0 c to +70 c) x
revision history revision date pages description o 03/30/04 1-21 initial advance information data sheet release idt71p74204 (2m x 8-bit), 71p74104 (2m x 9-bit), 71p74804 (1m x 18 x -bit) 71p74604 (512k x 36-bit) advance information 18 mb qdr ii sram burst of 4 commercial temperature range

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